`include "../../src/Control.v"

`timescale 1ps/1ps
module testbench;
    reg clk, reset;
    initial clk = 1;
    initial reset = 0;
    always #5 clk = ~clk;

    reg[6:0] InstructionOPCode;

    wire Branch;  //分支指令信号
    wire MemRead;  //读内存信号（load）
    wire MemtoReg;    //多路选择器控制信号（内存数还是ALUresult）
    wire[1:0] ALUop;   //ALU控制信号
    wire MemWrite;    //写内存信号
    wire ALUSrc;      //多路选择器控制信号（操作数还是立即数）
    wire RegWrite;    //允许写入寄存器信号

    initial
    begin
        #10 InstructionOPCode = 7'd1;
        #10 InstructionOPCode = 7'd2;
        #10 InstructionOPCode = 7'd3;
        #10 InstructionOPCode = 7'd4;
        #10 InstructionOPCode = 7'd5;
        #10 InstructionOPCode = 7'd6;
        #10 InstructionOPCode = 7'd7;
        #10 $stop;

    end

    Control U0(clk, reset, InstructionOPCode, 
                Branch, MemRead, MemtoReg, ALUop, MemWrite, ALUSrc, RegWrite);
    
    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end
endmodule